(1) Field of the Invention
The present invention relates to a method used to fabricate high density, semiconductor, DRAM cells, and more specifically to a process used to increase the surface area, and the accompanying capacitance of a stacked capacitor structure, via the use of hemispherical grain silicon.
(2) Description of the Prior Art
The semiconductor industry is continually striving to improve device performance, while still focusing on methods of reducing manufacturing costs. These objectives have been successfully addressed by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Sub-micron features allow the reduction in performance degrading capacitances and resistances to be realized. In addition the smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller, or sub-micron features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 64 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
One method of maintaining, or increasing STC capacitance, while still decreasing the lateral dimension of the capacitor, has been the use of rough, or hemispherical grained, (HSG), polysilicon layers. HSG polysilicon layers have been used as an overlying layer, on a conventional polysilicon structure, as shown by Dennison, in U.S. Pat. No. 5,340,763, and by Nagasawa, et al, in U.S. Pat. No. 5,444,653. The Dennison invention describes a storage node, or lower electrode, of an STC structure, in which the surface area of a polysilicon lower electrode structure is increased by deposition of an HSG polysilicon layer, on an insulator layer, which is overlying the top surface of the lower electrode structure. Subsequent etching procedures result in the transfer of the roughened surface, created by the HSG polysilicon layer, to only the top surface of the polysilicon lower electrode structure. The roughened, top surface of the polysilicon lower electrode, with the increased surface area, results in a capacitance increase for the subsequent capacitor structure. However the capacitance increase, realized in U.S. Pat. No. 5,340,763, is limited by subjecting only the top surface of the polysilicon lower electrode to the HSG polysilicon deposition and etch procedure, leaving the sides of the polysilicon lower electrode flat.
This invention will describe a process for increasing the surface area of a polysilicon lower electrode, or storage node electrode, by forming an HSG polysilicon layer only on the sides of the storage node electrode, while maintaining a flat, or non-roughened, top surface. This configuration is a result of using a silicon oxide hard mask, overlying the top surface of the lower electrode structure, therefore accepting the HSG polysilicon deposition. The use of the silicon oxide hard mask, prevents the deleterious attack of the polysilicon lower electrode structure, during an HSG polysilicon etch back procedure, performed to remove unwanted HSG polysilicon from non-capacitor regions. This invention will also offer another iteration in which HSG polysilicon-silicon oxide, hard mask features, are prepared on the top surface of a polysilicon lower electrode structure, than used as a mask, to remove polysilicon from the spaces exposed between the HSG polysilicon-silicon oxide features. The etch process results in a roughened, polysilicon lower electrode, top surface, and along with the HSG polysilicon coated sidewalls, offer greater surface area increases than counterparts fabricated with only roughened sides, or with only a roughened top surface.